The present invention relates to digital data processing, and more particularly to a serial dynamic memory shift register having an array configuration of dynamic memory cells that performs data shift operations with significantly fewer transistors than a conventional shift register.
The cell of a conventional shift register has a transfer device followed by an inverter followed by another transfer device followed by another inverter for a total of six to eight transistors per cell. Data is input to the first transfer device that is enabled by a first clock signal to pass the data to the first inverter. The output of the first inverter is clocked through the second transfer device by a second clock signal to the second inverter, the data being output from the second inverter delayed by one clock cycle where the two clock signals are opposite phases of a master clock signal. When the integration of several large shift registers on a single chip is required, this type of shift register cell is not economical. For instance the size of each shift register may be ten bits wide and one thousand bits long. If four of such registers are required on a single chip, the total number of transistors could exceed 320,000.
What is desired is a shift register that reduces the total number of transistors for a given size without a reduction in processing speed.